intel F-Tile Interlaken FPGA IDesign ExampJagorar Mai Amfani

 

An sabunta don Intel® Quartus® Prime Design Suite: 21.4
Shafin IP: 3.1.0

1. Jagorar farawa da sauri

F-Tile Interlaken Intel® FPGA IP core yana ba da benci na siminti da ƙirar ƙirar kayan masarufi.ampwanda ke goyan bayan haɗawa da gwajin kayan aiki. Lokacin da ka samar da zane exampHar ila yau, editan siga yana ƙirƙirar ta atomatik filewajibi ne don kwaikwaya, tattarawa, da gwada ƙira.

The testbench da zane exampLe yana goyan bayan yanayin NRZ da PAM4 don na'urorin F-tile.
F-Tile Interlaken Intel FPGA IP core yana haifar da ƙiraampLes don haɗin haɗin gwiwar masu zuwa na adadin hanyoyi da ƙimar bayanai.

Tebura 1. Haɗuwa da Tallafin IP na Yawan Layuka da Bayanan Bayanai
Ana tallafawa haɗe-haɗe masu zuwa a cikin sigar software ta Intel Quartus® Prime Pro Edition 21.4. Duka
sauran haɗin gwiwar za a tallafawa a cikin sigar Intel Quartus Prime Pro Edition na gaba.

 

Hoto 1. Matakan Ci gaba don Zane Example

(1) Wannan bambance-bambancen yana goyan bayan Yanayin Duba-gefe na Interlaken.
(2) Don ƙirar ƙirar layin 10, F-tile yana buƙatar hanyoyin 12 na TX PMA don ba da damar ɗaukar hoto mai haɗawa don rage skew tashoshi.

*Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

F-Tile Interlaken Intel FPGA IP core design example yana goyan bayan fasalulluka masu zuwa:

• TX na ciki zuwa yanayin madauki na RX
• Yana haifar da ƙayyadaddun fakiti masu girman kai ta atomatik
• Asalin damar duba fakiti
• Ikon yin amfani da Console System don sake saita ƙira don manufar sake gwadawa

Hoto 2. Tsarin Toshe Babban Matsayi

Bayanai masu alaƙa

• F-Tile Interlaken Intel FPGA IP Jagorar Mai Amfani
• F-Tile Interlaken Intel FPGA IP Bayanan Bayanin Sakin

1.1. Bukatun Hardware da Software
Don gwada tsohonampDon ƙira, yi amfani da hardware da software masu zuwa:

• Intel Quartus Prime Pro Edition software 21.4
• Akwai na'ura wasan bidiyo tare da Intel Quartus Prime Pro Edition software
• Na'urar kwaikwayo mai goyan baya:
  - Tambayoyi* VCS*
  - Takaddun shaida VCS MX
  - Siemens* EDA ModelSim* SE ko Questa*
  - Cadence* Xcelium*
• Intel Agilex™ I-Series Transceiver-SoC Development Kit

1.2. Samar da Zane
Hoto 3. Tsari

Bi waɗannan matakan don samar da ƙirar example da testbench:

1. A cikin Intel Quartus Prime Pro Edition software, danna File ➤ Sabon Project Wizard don ƙirƙirar sabon aikin Intel Quartus Prime, ko danna File ➤ Bude Project don buɗe aikin Intel Quartus Prime da ke gudana. Mayen yana tambayarka don saka na'ura.
2. Ƙayyade dangin Agilex na na'urar kuma zaɓi na'urar tare da F-Tile don ƙirar ku.
3. A cikin Catalog na IP, gano wuri kuma danna F-Tile Interlaken Intel FPGA IP sau biyu. Sabuwar taga Bambancin IP yana bayyana.
4. Ƙayyade sunan babban matakin don bambancin IP ɗin ku na al'ada. Editan siga yana adana saitunan bambancin IP a cikin a file mai suna .ip.
5. Danna Ok. Editan siga ya bayyana.

Hoto 4. Exampda Design Tab

6. A kan shafin IP, ƙayyade sigogi don bambancin ainihin IP ɗin ku.
7. Akan ExampDon Zane shafin, zaɓi zaɓin Simulation don ƙirƙirar bench. Zaɓi zaɓin Synthesis don samar da ƙirar kayan masarufi example. Dole ne ku zaɓi aƙalla ɗaya daga cikin zaɓuɓɓukan Simulation da Synthesis don samar da ƙirar ƙiraample.
8. Don Ƙirƙirar HDL Format, duka Verilog da VHDL zaɓi yana samuwa.
9. Don Kit ɗin Ci gaban Target, zaɓi Agilex I-Series Transceiver-SOC Development Kit.

Lura: Lokacin da kuka zaɓi zaɓin Kit ɗin Haɓakawa, ana saita ayyukan fil bisa ga lambar ɓangaren na'urar Intel Agilex I-Series Transceiver-SoC Development Kit (AGIB027R31B1E2VR0) kuma yana iya bambanta da na'urar da kuka zaɓa. Idan kuna da niyyar gwada ƙira akan hardware akan PCB daban, zaɓi Babu zaɓin kayan haɓakawa kuma kuyi ayyukan fil ɗin da suka dace a cikin .qsf file
10. Danna Generate Exampda Design. Zaɓi ExampTagar Zane Directory ya bayyana.
11. Idan kana so ka gyara zane examphanyar directory ko suna daga abubuwan da aka nuna (ilk_f_0_example_design), bincika zuwa sabuwar hanya kuma rubuta sabon ƙira exampda directory name.
12. Danna OK.

Lura: A cikin F-Tile Interlaken Intel FPGA IP ƙiraampHar ila yau, ana aiwatar da SystemPLL ta atomatik, kuma an haɗa shi zuwa F-Tile Interlaken Intel FPGA IP core. Hanyar matsayi na SystemPLL a cikin ƙira exampda ni:

example_design.test_env_inst.test_dut.dut.pll

The SystemPLL a cikin zane exampLe yana raba agogon tunani iri ɗaya na 156.26 MHz kamar Mai Canjawa.

1.3. Tsarin Jagora
F-Tile Interlaken Intel FPGA IP core yana haifar da masu zuwa files don zane
exampda:
Hoto 5. Tsarin Jagora

Tebura 2. Zane Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kayan Kasa na Ƙasa ta Duniyaample File Bayani
Wadannan files suna cikinample_installation_dir>/ilk_f_0_example_design directory.

Tebur 3. Testbench File Bayani
Wannan file yana cikinample_installation_dir>/ilk_f_0_example_design/example_design/rtl directory.

Tebur 4. Rubutun Testbench
Wadannan files suna cikinample_installation_dir>/ilk_f_0_example_design/example_design/testbench directory.

1.4. Simulating da Design Exampda Testbench
Hoto 6. Tsari

Bi waɗannan matakan don kwaikwaya testbench:

1. A saurin umarni, canza zuwa littafin simulations na testbench. Hanyar jagora ita ceample_installation_dir>/ misaliample_design/testbench.
2. Gudanar da rubutun simintin don goyan bayan na'urar kwaikwayo na zaɓinku. Rubutun yana tattarawa kuma yana gudanar da testbench a cikin na'urar kwaikwayo. Rubutun ku ya kamata ya duba cewa SOP da EOP ƙidaya sun dace bayan an gama simulation.

Tebur 5. Matakan Gudun Kwaikwayo

3. Yi nazarin sakamakon. Simulation mai nasara yana aikawa da karɓar fakiti, kuma yana nuna "GWAJI WUCE".
The testbench ga zane exampya kammala ayyuka masu zuwa:

• Yana ƙaddamar da F-Tile Interlaken Intel FPGA IP core.
• Yana buga halin PHY.
• Yana bincika aiki tare na metaframe (SYNC_LOCK) da iyakoki (toshe).
  (KALMOMI_LOCK).
• Yana jira a kulle da daidaita wayoyi guda ɗaya.
• Fara watsa fakiti.
• Duba kididdigar fakiti:
  - Kurakurai CRC24
  - SOPs
  - EOPs

Mai zuwa sampLe fitarwa yana kwatanta nasarar gwajin simulation:

Lura: Tsarin Interlaken example simulation testbench yana aika fakiti 100 kuma yana karɓar fakiti 100.

Mai zuwa sampLe fitarwa yana kwatanta nasarar gwajin simulation don yanayin kallon-gefe na Interlaken:

1.5. Ƙirƙirar da Ƙaddamar da Tsarin Hardware Example

1. Tabbatar da tsohonample zane tsara ya cika.
2. A cikin software na Intel Quartus Prime Pro Edition, buɗe aikin Intel Quartus Primeample_installation_dir>/ misaliample_design.qpf>.
3. A kan Gudanarwa menu, danna Fara Tari.
4. Bayan nasarar hadawa, a .sof file yana samuwa a cikin ƙayyadadden kundin adireshi.
   Bi waɗannan matakan don tsara kayan aikin example zane akan na'urar Intel Agilex tare da F-tile:
   a. Haɗa Kit ɗin Haɓakawa zuwa kwamfutar mai ɗaukar nauyi.
   b. Kaddamar da aikace-aikacen Ikon Agogo, wanda ke cikin kayan haɓakawa. Saita sababbin mitoci don ƙira exampda kamar haka:
   • Don yanayin NRZ:
   - Si5391 (U18), OUT0: Saita zuwa ƙimar pll_ref_clk(3) gwargwadon buƙatun ƙirar ku.
   • Don yanayin PAM:
   - Si5391 (U45), OUT1: Saita zuwa ƙimar pll_ref_clk(3) gwargwadon buƙatun ƙirar ku.
   - Si5391 (U19), OUT1: Saita zuwa ƙimar mac_pll_ref_clk(3) gwargwadon buƙatun ƙirar ku. c. Danna Tools
   d. Zaɓi na'urar shirye-shirye. Ƙara Intel Agilex I-Series Transceiver-SoC Development Kit.
   e. Tabbatar da haka Yanayin an saita zuwa JTAG.
   f. Zaɓi na'urar Intel Agilex I-Series kuma danna Ƙara Na'ura. Mai tsara shirye-shirye yana nuna zanen haɗin kai tsakanin na'urorin da ke kan allo.
   g. Duba akwatin don .sofa.
   h. Duba akwatin a cikin Shirin/Sanya shafi.
   i. Danna Fara.

1.6. Gwajin Tsarin Hardware Example
Bayan kun haɗa F-tile Interlaken Intel FPGA IP ƙirar misaliampda kuma saita na'urarka, za ka iya amfani da System Console don tsara ainihin IP da rajista.

Bi waɗannan matakan don kawo tsarin Console da gwada ƙirar kayan masarufiampda:

• Babu kurakurai don CRC32, CRC24, da mai duba.
• Ya kamata SOPs da EOPs da aka watsa su dace da SOPs da EOPs da aka karɓa.

Mai zuwa sampLe fitarwa yana kwatanta nasarar gwajin gwagwarmaya a yanayin Interlaken:

Mai zuwa sampLe fitarwa yana kwatanta nasarar gwajin gwagwarmaya a yanayin Interlaken Lookside:

 

2. Zane Example Bayanin

Zane example yana nuna ayyukan Interlaken IP core.

2.1. Zane ExampAbubuwan da aka gyara
The example zane yana haɗa tsarin da agogon tunani na PLL da abubuwan ƙira da ake buƙata. The example zane yana daidaita ainihin IP a cikin yanayin madauki na ciki kuma yana haifar da fakiti akan hanyar sadarwar mai amfani ta IP core TX. Babban IP ɗin yana aika waɗannan fakiti akan hanyar madauki na ciki ta hanyar mai karɓa.

Bayan mai karɓar ainihin IP ɗin ya karɓi fakiti akan hanyar madauki, yana aiwatar da fakitin Interlaken kuma yana watsa su akan hanyar musayar bayanan mai amfani na RX. The example zane yana bincika cewa fakitin da aka karɓa kuma sun watsa wasan.

F-Tile Interlaken Intel FPGA IP ƙira example ya ƙunshi abubuwa masu zuwa:

1. F-Tile Interlaken Intel FPGA IP core
2. Fakiti Generator da Fakiti Checker
3. Bayanin F-Tile da Tsarin PLL yana kulle Intel FPGA IP core

2.2. Zane Exampda Flow
F-Tile Interlaken Intel FPGA IP ƙirar kayan masarufi example kammala wadannan matakai:

1. Sake saita F-tile Interlaken Intel FPGA IP da F-Tile.
2. Saki sake saitin akan Interlaken IP (sake saitin tsarin) da F-tile TX (tile_tx_rst_n).
3. Yana saita F-tile Interlaken Intel FPGA IP a cikin yanayin madauki na ciki.
4. Saki sake saitin F-tile RX (tile_rx_rst_n).
5. Yana aika rafi na fakitin Interlaken tare da ƙayyadaddun bayanai a cikin abin da ake biya zuwa wurin musayar bayanan mai amfani na TX na tushen IP.
6. Yana duba fakitin da aka karɓa kuma ya ba da rahoton matsayin. Mai duba fakitin da aka haɗa a cikin ƙirar kayan masarufi example yana ba da damar duba fakiti masu zuwa:
   • Bincika cewa jerin fakitin da aka watsa daidai ne.
   Yana bincika cewa bayanan da aka karɓa sun yi daidai da ƙimar da ake tsammani ta hanyar tabbatar da farkon fakiti (SOP) da ƙarshen fakiti (EOP) suna daidaitawa yayin da ake watsa bayanai da karɓa.

*Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

2.3. Siginonin Sadarwa
Tebur 6. Zane Exampda Alamar Interface

2.4. Rajista taswira

Lura:

• Zane Exampadireshin rajista yana farawa da 0x20** yayin da adireshin IP na Interlaken ya fara da 0x10**.
• Adireshin rajista na F-tile PHY yana farawa da 0x30** yayin da adireshin F-tile FEC yana farawa da 0x40**. Ana samun rijistar FEC a yanayin PAM4 kawai.
• Lambar shiga: RO — Karanta Kawai, da RW — Karanta/Rubuta.
• Na'urar wasan bidiyo na tsarin tana karanta zanen exampLe yayi rijista kuma yayi rahoton matsayin gwajin akan allon.

Tebur 7. Zane Exampda Rajista taswira

Tebur 8. Zane Exampda Rijista taswira don Ƙirar Kallon Interlaken Example
Yi amfani da wannan taswirar rajista lokacin da kuke samar da ƙira examptare da Kunna siginar Duba-gefe na Interlaken.

2.5. Sake saiti
A cikin F-Tile Interlaken Intel FPGA IP core, kuna fara sake saiti (reset_n=0) kuma ku riƙe har sai ainihin IP ɗin ya dawo da sake saiti (reset_ack_n=0). Bayan an cire sake saiti (reset_n=1), amincewar sake saitin zai dawo zuwa yanayin farko (reset_ack_n=1). A cikin zane example, rajistar rst_ack_sticky tana riƙe da tabbacin sake saiti sannan kuma yana haifar da cire sake saiti (reset_n=1). Kuna iya amfani da madadin hanyoyin da suka dace da bukatun ƙirar ku.

Muhimmi: A kowane yanayi inda ake buƙatar madauki na ciki, dole ne ku saki TX da RX na F-tile daban a cikin takamaiman tsari. Koma zuwa rubutun na'ura mai kwakwalwa don ƙarin bayani.

Hoto 7. Sake saita Jeri a Yanayin NRZ

Hoto 8. Sake saita Jeri a Yanayin PAM4

 

3. F-Tile Interlaken Intel FPGA IP Design ExampRukunin Rubutun Jagorar Mai Amfani

Idan ba a jera sigar ainihin IP ba, jagorar mai amfani don sigar ainihin IP ta baya tana aiki.

 

4. Tarihin Bita na Takardu don F-Tile Interlaken Intel FPGA IP Design ExampJagorar Mai Amfani

 

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aikin FPGA da samfuran semiconductor zuwa na yanzu
ƙayyadaddun bayanai daidai da daidaitaccen garantin Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.

 

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