intel Interlaken 2nd Gen FPGA IP Bayanan Bayanin Sakin
Interlaken (ƙarni na biyu) Intel® FPGA IP Bayanan Bayani na Sakin
Idan bayanin kula ba ya samuwa don takamaiman sigar ainihin IP, asalin IP ɗin ba shi da canje-canje a cikin wannan sigar. Don bayani game da sabuntawar IP har zuwa v18.1, koma zuwa Bayanan Bayanin Sakin Sabuntawa na Intel Quartus Prime Design Suite. Siffofin IP na Intel® FPGA sun dace da nau'ikan software na Intel Quartus® Prime Design Suite har zuwa v19.1. An fara a cikin sigar software ta Intel Quartus Prime Design Suite 19.2, Intel FPGA IP yana da sabon tsarin siga. Lambar Intel FPGA IP (XYZ) na iya canzawa tare da kowace sigar software ta Intel Quartus Prime. Canji a:
- X yana nuna babban bita na IP. Idan kun sabunta Intel Quartus Prime software, dole ne ku sake haɓaka IP ɗin.
- Y yana nuna IP ɗin ya ƙunshi sabbin abubuwa. Sake haɓaka IP ɗin ku don haɗa waɗannan sabbin fasalolin.
- Z yana nuna IP ɗin ya ƙunshi ƙananan canje-canje. Sake haɓaka IP ɗin ku don haɗa waɗannan canje-canje.
- Intel Quartus Prime Design Suite Sabunta Bayanan Bayanan Sakin
- Interlaken (2nd Generation) Intel FPGA IP Jagorar Mai amfani
- Errata don Interlaken (2nd Generation) Intel FPGA IP a cikin Tushen Ilimi
- Interlaken (ƙarni na biyu) Intel Stratix 2 FPGA IP Design ExampJagorar Mai Amfani
- Interlaken (ƙarni na biyu) Intel Agilex FPGA IP Design ExampJagorar Mai Amfani
- Gabatarwa zuwa Intel FPGA IP Cores
Interlaken (ƙarni na biyu) Intel FPGA IP v2
Table 1. v20.0.0 2020.10.05
| Intel Quartus Prime Version | Bayani | Tasiri |
|
20.3 |
Ƙara tallafi don ƙimar bayanan 25.78125 Gbps. | - |
| Canza tallafin ƙimar bayanai daga 25.3 Gbps zuwa 25.28 Gbps da 25.8 Gbps zuwa 25.78125 Gbps. |
- |
Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
Ana iya da'awar wasu sunaye da alamun a matsayin mallakin wasu.
Interlaken (ƙarni na biyu) Intel FPGA IP v2
Table 2. v19.3.0 2020.06.22
| Intel Quartus Prime Version | Bayani | Tasiri |
|
19.3.0 |
IP ɗin yanzu yana goyan bayan fasalin kallon-gefe na Interlaken. | - |
| An ƙara sabo Kunna yanayin Duba-gefe na Interlaken parameter a cikin editan sigar IP. | Kuna iya saita IP ɗin a cikin yanayin Duba-gefe na Interlaken. | |
| Zaɓin yanayin canja wuri Ana cire siga daga sigar Intel Quartus Prime software na yanzu. |
- |
|
| Ƙara tallafin ƙimar bayanai na 12.5 Gbps don adadin hanyoyi 10 a cikin H-tile da E-tile (yanayin NRZ) bambance-bambancen ainihin IP. |
- |
|
| An cire sigina masu zuwa daga IP:
• rx_pma_data • tx_pma_data • jin_yunwa • jin_yunwa |
- |
|
| Ƙara waɗannan sabbin sigina:
• sop_cntr_inc1 • eop_cntr_inc1 • rx_xcoder_uncor_feccw • itx_ch0_xon • irx_ch0_xon • itx_ch1_xon • irx_ch1_xon • itx_mai inganci • irx_valid • rashin aiki • irx_idle • itx_ctrl • itx_credit • irx_credit |
- |
|
| Cire abubuwan biya guda biyu daga taswirar rajista:
• 16'h40- TX_READY_XCVR • 16'h41- RX_READY_XCVR |
- |
|
| Gwajin kayan aiki na zane exampLe yana samuwa yanzu don na'urorin Intel Agilex™. | Kuna iya gwada ƙirar ƙiraampa kan Intel Agilex F- jerin Transceiver-SoC Development Kit. | |
| Kuna iya canza ƙimar bayanai da mitar agogo mai jujjuyawa zuwa ƙima daban-daban don misalin IP ɗin ku na Interlaken (2nd Generation) wanda ke hari Intel Stratix® 10 H-tile ko na'urar E-tile. Koma zuwa wannan KDB don bayani kan yadda ake canza ƙimar bayanai. |
Kuna iya keɓance ƙimar bayanai dangane da fale-falen fale-falen. |
Interlaken (ƙarni na biyu) Intel FPGA IP v2
Table 3. v19.2.1 2019.09.27
| Intel Quartus Prime Version | Bayani | Tasiri |
|
19.3 |
Sakin jama'a don na'urorin Intel Agilex tare da masu jigilar E-tile. | - |
| Sake suna Interlaken (2nd Generation) Intel Stratix 10 FPGA IP zuwa Interlaken (2nd Generation) Intel FPGA IP |
- |
Interlaken (ƙarni na biyu) Intel Stratix 2 FPGA IP v10 Sabunta 18.1
Table 4. Shafin 18.1 Sabuntawa 1 2019.03.15
| Bayani | Tasiri |
| Ƙara goyon bayan yanayin sassa da yawa. | - |
| Kara Yawan Ƙungiyoyi siga. | - |
| • Ƙara tallafi don haɗin layi da ƙimar bayanai kamar haka:
- Don na'urorin Intel Stratix 10 L-tile: • Hanyoyi 4 tare da ƙimar layin 12.5/25.3/25.8 Gbps • Hanyoyi 8 tare da ƙimar layin 12.5 Gbps - Don na'urorin Intel Stratix 10 H-tile: • Hanyoyi 4 tare da ƙimar layin 12.5/25.3/25.8 Gbps • Hanyoyi 8 tare da ƙimar layin 12.5/25.3/25.8 Gbps • Hanyoyi 10 tare da ƙimar layin 25.3/25.8 Gbps - Don na'urorin Intel Stratix 10 E-tile (NRZ): • Hanyoyi 4 tare da ƙimar layin 6.25/12.5/25.3/25.8 Gbps • Hanyoyi 8 tare da ƙimar layin 12.5/25.3/25.8 Gbps • Hanyoyi 10 tare da ƙimar layin 25.3/25.8 Gbps • Hanyoyi 12 tare da ƙimar layin 10.3125 Gbps |
- |
| • Ƙara sabbin siginoni masu watsawa na mai amfani:
- shix_eob1 - itx_eopbits1 - shi_chan1 |
- |
| • Ƙara sabbin sigina masu mu'amala da mai karɓa:
- irx_eob1 - irx_eopbits1 - irx_chan1 - irx_err1 - irx_err |
- |
Interlaken (ƙarni na biyu) Intel Stratix 2 FPGA IP v10
Table 5. Shafin 18.1 2018.09.10
| Bayani | Tasiri | Bayanan kula |
| Sake suna tayal ɗin takaddar azaman Interlaken (ƙarni na biyu) Intel Stratix 2 FPGA IP Jagorar Mai amfani |
- |
- |
| Ƙara samfurin kwaikwayo na VHDL da goyan bayan testbench don Interlaken (2nd Generation) IP core. |
- |
- |
| An ƙara sabbin rajista masu zuwa zuwa ainihin IP: | ||
| • TX_READY_XCVR | ||
| • RX_READY_XCVR
• ILKN_FEC_XCODER_TX_ILLEGAL_ JIHAR |
- | Waɗannan rajistar suna samuwa ne kawai a cikin bambancin na'urar Intel Stratix 10 E-Tile. |
| • ILKN_FEC_XCODER_RX_ILLEGAL_ JIHAR |
Interlaken (ƙarni na biyu) Intel FPGA IP v2
Table 6. Shafin 18.0.1 Yuli 2018
| Bayani | Tasiri | Bayanan kula |
| Ƙara tallafi don na'urorin Intel Stratix 10 tare da masu karɓar E-Tile. |
- |
- |
| An ƙara tallafin ƙimar bayanai na 53.125 Gbps don Intel Stratix 10 E-Tile na'urorin a cikin yanayin PAM4. |
- |
- |
| Ƙara siginar agogo mac_clkin don Intel Stratix 10 E-Tile na'urorin a cikin yanayin PAM4 |
- |
- |
Interlaken (ƙarni na biyu) Intel FPGA IP v2
Table 7. Shafin 18.0 Mayu 2018
| Bayani | Tasiri | Bayanan kula |
| Sake suna Interlaken IP core (2nd Generation) zuwa Interlaken (2nd Generation) Intel FPGA IP kamar yadda ake sake suna Intel. |
- |
- |
| An ƙara tallafin ƙimar bayanan 25.8 Gbps don adadin hanyoyi 6 da 12. |
- |
- |
| Ƙara goyon baya don Cadence Xcelium* Simulator na layi ɗaya. |
- |
- |
Interlaken IP Core (ƙarni na biyu) v2
Table 8. Shafin 17.1 Nuwamba 2017
| Bayani | Tasiri | Bayanan kula |
| Sakin farko a cikin Laburaren IP na Intel FPGA. | - | - |
Bayanai masu alaƙa
Interlaken IP Core (2nd Generation) Jagorar mai amfani
Interlaken (ƙarni na biyu) Rukunin Jagorar Mai Amfani na Intel FPGA
| Sigar Quartus | IP Core Version | Jagorar Mai Amfani |
| 20.2 | 19.3.0 | Interlaken (ƙarni na biyu) FPGA IP Jagorar mai amfani |
| 19.3 | 19.2.1 | Interlaken (ƙarni na biyu) FPGA IP Jagorar mai amfani |
| 19.2 | 19.2 | Interlaken (ƙarni na biyu) FPGA IP Jagorar mai amfani |
| 18.1.1 | 18.1.1 | Interlaken (ƙarni na biyu) Intel Stratix 2 FPGA IP Jagorar Mai amfani |
| 18.1 | 18.1 | Interlaken (ƙarni na biyu) Intel Stratix 2 FPGA IP Jagorar Mai amfani |
| 18.0.1 | 18.0.1 | Interlaken (ƙarni na biyu) FPGA IP Jagorar mai amfani |
| 18.0 | 18.0 | Interlaken (2nd Generation) Intel FPGA IP Jagorar Mai amfani |
| 17.1 | 17.1 | Interlaken IP Core (2nd Generation) Jagorar mai amfani |
Sifofin IP iri ɗaya ne da nau'ikan software na Intel Quartus Prime Design Suite har zuwa v19.1. Daga Intel Quartus Prime Design Suite software version 19.2 ko kuma daga baya, IP cores suna da sabon tsarin sigar IP. Idan ba a jera sigar ainihin IP ba, jagorar mai amfani don sigar ainihin IP ta baya tana aiki.
Takardu / Albarkatu
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intel Interlaken 2nd Gen FPGA IP Bayanan Bayanin Sakin [pdf] Umarni Interlaken 2nd Gen FPGA IP Bayanan kula na Sakin, Interlaken 2nd Gen, Bayanan Sakin IP na FPGA |
