Low Latency E-Tile 40G Ethernet Intel FPGA IP Design Example
Jagoran Fara Mai Sauri
Low Latency E-Tile 40G Ethernet Intel® FPGA IP core yana ba da gwajin siminti da ƙirar ƙirar kayan masarufi.ampwanda ke goyan bayan haɗawa da gwajin kayan aiki. Lokacin da ka samar da zane exampHar ila yau, editan sigar IP na Intel Quartus® Prime yana ƙirƙirar ta atomatik fileya zama dole don kwaikwaya, tarawa, da gwada ƙira a cikin kayan masarufi. Bugu da kari, zaku iya zazzage ƙirar kayan masarufi da aka haɗa zuwa ƙayyadaddun kayan haɓakawa na na'urar Intel don gwajin haɗin gwiwa. Intel FPGA IP kuma ya haɗa da tarin-kawai tsohonampaikin da za ku iya amfani da shi don kimanta yankin ainihin IP da lokaci da sauri. Low Latency E-Tile 40G Ethernet Intel FPGA IP yana goyan bayan ƙira example tsara tare da fadi da kewayon sigogi. Duk da haka, da zane exampba sa rufe duk yuwuwar ma'auni na Low Latency E-Tile 40G Ethernet Intel FPGA IP Core.
Matakan haɓaka don Zane Example
Bayanai masu alaƙa
- Low Latency E-Tile 40G Ethernet Intel FPGA IP Jagorar Mai Amfani
Don cikakkun bayanai akan Low Latency E-Tile 40G Ethernet IP. - Ƙananan Latency E-Tile 40G Ethernet Intel FPGA IP Bayanan Bayanin Sakin
Bayanan Bayanin Sakin IP ya lissafa canje-canjen IP a cikin wani saki na musamman.
Samar da Zane Example
Tsari
Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. Ana iya da'awar wasu sunaye da alamun a matsayin mallakin wasu.
ExampShafi Zane a cikin Ƙananan Latency E-Tile 40G Ethernet Parameter Editan
Zaɓi Stratix 10 TX E-Tile Transceiver Siginar Haɓaka Mutuncin Haɓaka Kit don samar da tsohon ƙiraampdon na'urorin Intel Stratix® 10. Zaɓi Agilex F-jerin Transceiver-SoC Development Kit don samar da ƙira exampdon na'urorin Intel Agilex™.
Bi waɗannan matakan don samar da ƙirar kayan masarufi example da testbench:
- A cikin Intel Quartus Prime Pro Edition software, danna File ➤ Sabon Mayen Aikin
don ƙirƙirar sabon aikin Intel Quartus Prime, ko File ➤ Bude Project don buɗe aikin software na Intel Quartus Prime. Mayen yana tambayarka don saka dangi da na'ura.
Lura: Zane example overwrites zabin da na'urar a kan manufa jirgin. Kuna saka allon manufa daga menu na ƙira exampzažužžukan a cikin Example Design tab (Mataki na 8). - A cikin Catalog na IP, gano wuri kuma zaɓi Low Latency E-Tile 40G Ethernet Intel FPGA IP. Sabuwar taga Bambancin IP yana bayyana.
- Ƙayyade sunan babban matakin don bambancin IP na al'ada. Editan madaidaicin IP na Intel Quartus Prime yana adana saitunan bambancin IP a cikin a file mai suna .ip.
- Danna Ok. Editan sigar IP yana bayyana.
- A shafin IP, ƙididdige sigogi don ainihin bambancin IP ɗin ku.
Lura: The Low Latency E-Tile 40G Ethernet Intel FPGA IP zane example baya yin kwaikwaya daidai kuma baya aiki daidai idan kun ayyana kowane ɗayan waɗannan sigogi:- Kunna preamble wucewa ta kunna
- An saita jinkirin da aka shirya zuwa ƙimar 3
- Kunna shigar TX CRC a kashe
- A kan Exampshafin Zane, ƙarƙashin Exampda Design Files, ba da damar zaɓin Simulation don samar da testbench, kuma zaɓi zaɓi na Synthesis don samar da tarin-kawai da ƙirar ƙirar hardware.amples.
Lura: Na ExampTa Zane shafin, ƙarƙashin Ƙirƙirar HDL Format, Verilog HDL kawai yana samuwa. Wannan tushen IP baya goyan bayan VHDL. - A karkashin Target Bude Ci gaba Zabi Stratix 10 TX E-Tile Transpeiver Sigilal Kit ko kuma Agilex f-jerin abubuwan cigaban ci gaba.
Lura: Kayan haɓakawa da kuka zaɓa yana sake rubuta zaɓin na'urar a Mataki- Intel Stratix 10 E-tile manufa na'urar shine 1SG280LU3F50E3VGS1.
- Manufar na'urar Intel Agilex E-tile shine AGFB014R24A2E2VR0.
- Danna Generate Example Design button. Zaɓi ExampTagar Zane Directory ya bayyana.
- Idan kana so ka gyara zane examphanyar shugabanci ko suna daga abubuwan da aka nuna (alt_e40c3_0_example_design), bincika zuwa sabuwar hanya kuma rubuta sabon ƙira exampsunan directory (ample_dir>).
- Danna Ok.
Bayanai masu alaƙa
- IP Core Parameters
Yana ba da ƙarin bayani game da keɓance ainihin adireshin IP ɗin ku. - Intel Stratix 10 E-Tile TX Siginar Mutuncin Haɓaka Kit
- Intel Agilex F-Series FPGA Development Kit
Zane Exampda Parameters
Ma'auni a cikin Exampda Design Tab
| Siga | Bayani |
| Zaɓi Zane | Akwai exampda zayyana don saitunan sigar IP. Lokacin da kuka zaɓi ƙira daga ɗakin karatu da aka saita, wannan filin yana nuna ƙirar da aka zaɓa. |
| Exampda Design Files | The files don samarwa don nau'ikan ci gaba daban-daban.
• kwaikwayo- yana haifar da wajibi files don simulating exampzane. • Magana- yana haifar da haɗakarwa files. Yi amfani da waɗannan files don tattara ƙira a cikin Intel Quartus Prime Pro software software don gwajin kayan aiki da yin nazarin lokaci mai tsayi. |
| Ƙirƙira File Tsarin | Tsarin RTL files don kwaikwayo-Verilog ko VHDL. |
| Zaɓi Board | Kayan aikin tallafi don aiwatar da ƙira. Lokacin da ka zaɓi hukumar haɓaka Intel, da Na'urar Target ita ce wacce ta dace da na'urar akan Kit ɗin Haɓakawa.
Idan babu wannan menu, babu allon tallafi don zaɓuɓɓukan da kuka zaɓa. Agilex F-jerin Transceiver-SoC Development Kit: Wannan zaɓi yana ba ku damar gwada ƙirar ƙiraample a kan zaɓaɓɓen kayan haɓaka IP na Intel FPGA. Wannan zaɓi yana zaɓar ta atomatik Na'urar Target Saukewa: AGFB014R24A2E2VR0. Idan bita na hukumar yana da nau'in na'ura daban-daban, zaku iya canza na'urar da aka yi niyya. |
| ci gaba… | |
| Siga | Bayani |
| Stratix 10 TX E-Tile Transceiver Siginar Mutunci Haɓaka Kit: Wannan zaɓi yana ba ku damar gwada ƙirar ƙiraample a kan zaɓaɓɓen kayan haɓaka IP na Intel FPGA. Wannan zaɓi yana zaɓar ta atomatik Na'urar Target Saukewa: 1ST280EY2F55E2VG. Idan bita na hukumar yana da nau'in na'ura daban-daban, zaku iya canza na'urar da aka yi niyya.
Babu: Wannan zaɓin ya keɓance sassan kayan masarufi don ƙirar ƙirarample. |
Tsarin Jagora
Low Latency E-Tile 40G Ethernet IP core design example file kundin adireshi ya ƙunshi abubuwan da aka samar files don zane example.
Tsarin Jagora don Ƙirƙirar Zane Example
- Simulation files (testbench don kwaikwayo kawai) suna cikinample_dir>/ misaliample_testbench.
- Tarin-kawai example design yana cikinample_dir>/ compilation_test_design.
- Tsarin hardware da gwaji files (ƙirar kayan masarufi example) suna cikinample_dir>/hardware_test_design
Directory da File Bayani
| File Sunaye | Bayani |
| eth_ex_40g.qpf | Intel Quartus Prime aikin file. |
| eth_ex_40g.qsf | Saitunan ayyukan Intel Quartus Prime file. |
| ci gaba… | |
| File Sunaye | Bayani |
| eth_ex_40g.sdc | Synopsys* Matsalolin ƙira file. Kuna iya kwafa da gyara wannan file don ƙananan Latency E-Tile 40G Ethernet Intel FPGA IP ƙira. |
| eth_ex_40g.srf | Intel Quartus Prime ka'idar kashe saƙon aikin file. |
| eth_ex_40g.v | Babban matakin ƙirar Verilog HDL example file. |
| eth_ex_40g_clock.sdc | Ƙuntataccen Ƙira na Synopsys file don agogo. |
| gama gari/ | Hardware zane exampda goyon baya files. |
| hwtest/main.tcl | Babban file don samun damar System Console. |
Simulating da Design Exampda Testbench
Kuna iya haɗawa da kwaikwayi ƙirar ta hanyar gudanar da rubutun kwaikwayo daga saurin umarni.
- A saurin umarni, canza kundin aiki zuwaample_dir>/ misaliample_testbench.
- Gudanar da rubutun simintin don goyan bayan na'urar kwaikwayo na zaɓinku. Rubutun yana tattarawa kuma yana gudanar da testbench a cikin na'urar kwaikwayo
Umarnin don Kwaikwayi Testbench
| Na'urar kwaikwayo | Umarni |
| Model* | A cikin layin umarni, rubuta vsim -do run_vsim.do.
Idan kun fi son yin kwaikwayo ba tare da kawo ModelSim GUI ba, rubuta vsim -c -do run_vsim.do. Lura: ModelSim-AE da ModelSim-ASE na'urar kwaikwayo ba za su iya kwaikwayi wannan ainihin IP ba. Dole ne ku yi amfani da wani goyan bayan ModelSim na'urar kwaikwayo kamar ModelSim SE. |
| VCS* | A cikin layin umarni, rubuta sh run_vcs.sh |
| Farashin VCS MX | A cikin layin umarni, rubuta sh run_vcsmx.sh.
Yi amfani da wannan rubutun lokacin da ƙirar ta ƙunshi Verilog HDL da System Verilog tare da VHDL. |
| NCsim | A cikin layin umarni, rubuta sh run_ncsim.sh |
| Xcelium* | A cikin layin umarni, rubuta sh run_xcelium.sh |
Nasarar kwaikwayo ta ƙare tare da saƙo mai zuwa: An Ƙirar Simulators. ko Testbench cikakke. Bayan nasarar kammalawa, zaku iya tantance sakamakon.
Ƙirƙirar da Ƙaddamar da Zane Exampa cikin Hardware
Editan madaidaicin madaidaicin Intel FPGA IP yana ba ku damar haɗawa da daidaita ƙirar ƙiraampa kan kayan haɓakawa da aka yi niyya
Don haɗawa da daidaita ƙirar ƙira exampa kan hardware, bi waɗannan matakan:
- Kaddamar da Intel Quartus Prime Pro Edition software kuma zaɓi Processing ➤ Fara Tari don haɗa ƙira.
- Bayan kun ƙirƙiri abin SRAM file .sof, bi waɗannan matakan don tsara kayan ƙirar kayan aikin exampa kan na'urar Intel:
- Zaɓi Kayan aiki ➤ Mai Shirya shirye-shirye.
- A cikin Programmer, danna Saitin Hardware.
- Zaɓi na'urar shirye-shirye.
- Zaɓi kuma ƙara allon Intel TX zuwa zaman Intel Quartus Prime Pro Edition ɗin ku.
- Tabbatar cewa an saita Yanayin zuwa JTAG.
- Zaɓi na'urar Intel kuma danna Ƙara Na'ura. Mai Shirya shirye-shirye yana nuna zanen toshewar haɗin kai tsakanin na'urorin da ke kan allo.
- A cikin jere tare da sof ɗinku, duba akwatin don .sof.
- Kunna zaɓin Shirin/Sanya don .sof.
- Danna Fara.
Bayanai masu alaƙa
- Ƙirƙirar Ƙarfafa don Tsari da Ƙirar Ƙungiya
- Shirye-shiryen na'urorin Intel FPGA
Canza Na'urar Target a Tsarin Hardware Example
Idan kun zaɓi Stratix 10 TX E-Tile Transceiver Signal Integrity Development Kit azaman na'urar da kuka yi niyya, Low Latency E-Tile 40G Ethernet Intel FPGA IP core yana haifar da tsohon kayan aiki.ample zane don manufa na'urar 1ST280EY2F55E2VG. Idan kun zaɓi Agilex F-jerin Transceiver-SoC Development Kit azaman na'urar da kuka yi niyya, Low Latency E-Tile 40G Ethernet Intel FPGA IP core yana haifar da tsohon kayan aiki.ampBayani na AGFB014R24A2E2VR0. Ƙayyadadden na'urar da aka yi niyya na iya bambanta da na'urar da ke kan kayan haɓaka ku. Don canza na'urar da aka yi niyya a cikin ƙirar kayan aikinku exampko, bi waɗannan matakan:
- Kaddamar da Intel Quartus Prime Pro Edition software kuma buɗe aikin gwajin hardware file /hardware_test_design/eth_ex_40g.qpf.
- A menu na Ayyuka, danna Na'ura. Akwatin maganganu na na'ura yana bayyana.
- A cikin akwatin maganganu na Na'ura, zaɓi Teburin na'ura mai tushe na E-tile wanda yayi daidai da lambar ɓangaren na'urar akan kayan haɓakawa. Koma hanyar haɗin kayan haɓakawa akan Intel webshafin don ƙarin bayani.
- Gaggawa yana bayyana lokacin da kuka zaɓi na'ura, kamar yadda aka nuna a hoton da ke ƙasa. Zaɓi A'a don adana ayyukan fil da aka ƙirƙira da ayyukan I/O.
Intel Quartus Prime Prompt don Zaɓin Na'urar
- Yi cikakken tsarin ƙirar ku.
Yanzu zaku iya gwada ƙira akan kayan aikin ku.
Bayanai masu alaƙa
- Intel Stratix 10 E-Tile TX Siginar Mutuncin Haɓaka Kit
- Intel Agilex F-Series FPGA Development Kit
Gwada Low Latency E-Tile 40G Ethernet Intel FPGA IP Design a cikin Hardware
Bayan kun haɗa Low Latency E-Tile 40G Ethernet Intel FPGA IP core design exampda kuma saita shi akan na'urar Intel ɗin ku, zaku iya amfani da System Console don tsara ainihin IP da maƙallan Native PHY IP core rajista. Don kunna System Console da gwada ƙirar kayan masarufi exampko, bi waɗannan matakan:
- A cikin software na Intel Quartus Prime Pro Edition, zaɓi Kayan aiki ➤ Kayan aikin gyara gyara tsarin ➤ System Console don ƙaddamar da na'ura mai kwakwalwa.
- A cikin rukunin Tcl Console, rubuta cd hwtest don canza shugabanci zuwa /hardware_test_design/hwtest.
- Buga tushen main.tcl don buɗe haɗi zuwa JTAG maigida.
Ƙarin ƙira exampAna samun umarni don tsara tushen IP:
- chkphy_status: Yana Nuna mitocin agogo da matsayin kulle PHY.
- chkmac_stats: Nuna dabi'u a cikin ƙididdigar ƙididdigar MAC.
- share_all_stats: Yana share masu ƙididdige ƙididdiga na IP.
- fara_pkt_gen: Fara janareta fakiti.
- tsaya_pkt_gen: Yana tsayar da janareta na fakiti.
- sys_reset_digital_analog: Sake saitin tsarin.
- madauki: Yana kunna madauki serial na ciki
- loop_off: Yana kashe madauki na ciki serial.
- reg_karatu : Yana dawo da ƙimar rajistar ainihin IP a .
- reg_rubutu : Ya rubuta zuwa IP core rajista a adireshin .
Bi tsarin gwaji a sashin Gwajin Hardware na ƙira example kuma duba sakamakon gwajin a cikin System Console.
Bayanai masu alaƙa
Nazari da Gyara Zane-zane tare da Console System
Zane Example Bayanin
E-tile na tushen 40G Ethernet ƙirar misaliample yana nuna ayyukan Low Latency E-Tile 40G Ethernet Intel FPGA IP core, tare da E-tile based transceiver interface mai dacewa da ƙayyadaddun IEEE 802.3ba daidaitaccen CAUI-4. Kuna iya samar da zane daga Example Design tab a cikin Low Latency E-Tile 40G Ethernet Intel FPGA IP editan siga.
Don samar da zane exampDon haka, dole ne ka fara saita ƙimar sigina don bambancin ainihin IP ɗin da kake son samarwa a ƙarshen samfurinka. Samar da ƙira example ƙirƙirar kwafin tushen IP; da testbench da hardware design exampYi amfani da wannan bambancin azaman DUT. Idan baku saita ma'auni don DUT don dacewa da ma'auni a cikin samfurin ƙarshenku ba, ƙirar ƙirar.ampda ka ƙirƙira baya motsa jiki da IP core bambancin da kuke nufi.
Lura:
Testbench yana nuna gwajin asali na ainihin IP. Ba a nufin ya zama madadin cikakken yanayin tabbatarwa ba. Dole ne ku yi ƙarin tabbataccen tabbaci na ƙaramin Latency E-Tile 40G Ethernet Intel FPGA IP ƙira a cikin kwaikwaiyo da cikin kayan aiki.
Siffofin
- Yana goyan bayan 40G Ethernet MAC/PCS IP core don E-tile transceiver ta amfani da Intel Stratix 10 ko Intel Agilex na'urar.
- Yana goyan bayan preamble wucewa-ta horo da haɗin kai.
- Yana haifar da ƙira exampda MAC statistics counters alama.
- Yana ba da testbench da rubutun kwaikwayo.
Bukatun Hardware da Software
Don gwada tsohonampDon ƙira, yi amfani da hardware da software masu zuwa:
- Intel Quartus Prime Pro Edition software
- Tsarin Console
- ModelSim, VCS, VCS MX, NCSim, ko Xcelium Simulator
- Intel Stratix 10 TX E-Tile Transceiver Siginar Haɓaka Mutuncin Haɓaka Kit ko Intel Agilex F-jerin Transceiver-SoC Development Kit
Bayanin Aiki
Wannan sashe yana bayyana 40G Ethernet MAC/PCS IP core ta amfani da na'urar Intel a cikin E-tile based transceiver. A cikin jagorar watsawa, MAC na karɓar firam ɗin abokin ciniki kuma yana saka tazarar fakiti (IPG), preamble, farkon ƙayyadaddun firam (SFD), padding, da raƙuman CRC kafin tura su zuwa PHY. PHY yana ɓoye firam ɗin MAC kamar yadda ake buƙata don ingantaccen watsawa akan kafofin watsa labarai zuwa ƙarshen nesa. A cikin hanyar karɓa, PHY yana wucewa da firam zuwa MAC. MAC na karɓar firam daga PHY, yin cak, fitar da CRC, preamble, da SFD, kuma yana ba da sauran firam ɗin ga abokin ciniki.
kwaikwayo
The testbench aika zirga-zirga ta hanyar IP core, motsa jiki da watsa gefe da karɓar gefen IP core.
Low Latency E-Tile 40G Ethernet Design Exampda Block zane
Tsarin simulation example babban matakin gwajin file shine basic_avl_tb_top.sv. Wannan file yana ba da nunin agogo clk_ref na 156.25Mhz zuwa PHY. Ya haɗa da ɗawainiya don aikawa da karɓar fakiti 10.
Low Latency E-Tile 40G Ethernet Core Testbench File Bayani
| File Sunaye | Bayani |
| Testbench da Simulation Files | |
| Basic_avl_tb_top.sv | Babban matakin gwajin benci file. Testbench yana ƙaddamar da DUT kuma yana gudanar da ayyukan Verilog HDL don samarwa da karɓar fakiti. |
| Basic_avl_tb_top_nc.sv | Babban matakin gwajin benci file mai jituwa tare da na'urar kwaikwayo ta NCSim. |
| basic_avl_tb_top_msim.sv | Babban matakin gwajin benci file mai jituwa tare da na'urar kwaikwayo ta ModelSim. |
| Rubutun Testbench | |
| run_vsim.do | Hotunan Jagora * Rubutun Sim don gudanar da benci. |
| run_vcs.sh | Rubutun Synopsys VCS don gudanar da gwajin benci. |
| ci gaba… | |
| File Sunaye | Bayani |
| run_vcsmx.sh | Rubutun Synopsys VCS MX (haɗe Verilog HDL da System Verilog tare da VHDL) don gudanar da benci. |
| run_ncsim.sh | Rubutun Cadence NCsim don gudanar da testbench. |
| run_xcelium.sh | Rubutun Cadence Xcelium don gudanar da testbench. |
Gudun gwajin nasara yana nuna fitarwa mai tabbatar da halaye masu zuwa:
- Ana jira agogon RX ya daidaita
- Buga halin PHY
- Ana aika fakiti 10
- Ana karɓar fakiti 10
- Nuna "Testbench cikakke."
Mai zuwa sampLe fitarwa yana kwatanta nasarar gwajin simulation:
- # Jiran daidaita RX
- #RX deskew a kulle
- An kulle layin #RX
- An kunna #TX
- #**Aika Fakiti 1…
- #**Aika Fakiti 2…
- #**Aika Fakiti 3…
- #**Aika Fakiti 4…
- #**Aika Fakiti 5…
- #**Aika Fakiti 6…
- #**Aika Fakiti 7…
- #**An Karɓi Fakiti 1…
- #**Aika Fakiti 8…
- #**An Karɓi Fakiti 2…
- #**Aika Fakiti 9…
- #**An Karɓi Fakiti 3…
- #**Aika Fakiti 10…
- #**An Karɓi Fakiti 4…
- #**An Karɓi Fakiti 5…
- #**An Karɓi Fakiti 6…
- #**An Karɓi Fakiti 7…
- #**An Karɓi Fakiti 8…
- #**An Karɓi Fakiti 9…
- #**An Karɓi Fakiti 10…
Bayanai masu alaƙa
Simulating da Design Example Testbench a shafi na 7
Gwajin Hardware
A cikin kayan aikin hardware exampHar ila yau, za ku iya tsara ainihin IP a cikin yanayin madauki na ciki da kuma samar da zirga-zirga a gefen watsawa wanda ke dawowa ta hanyar karɓa.
Low Latency E-Tile 40G Ethernet IP Hardware Design Example High Level Block zane
Ƙananan Latency E-Tile 40G Ethernet ƙirar ƙirar kayan aikin example ya ƙunshi abubuwa masu zuwa:
- Low Latency E-Tile 40G Ethernet Intel FPGA IP core.
- Hankalin abokin ciniki wanda ke daidaita shirye-shiryen tushen tushen IP, da tsara fakiti da dubawa.
- IOPLL don samar da agogon 100 MHz daga agogon shigarwar 50 MHz zuwa ƙirar kayan masarufi.ample.
- JTAG mai sarrafawa wanda ke sadarwa tare da Intel System Console. Kuna sadarwa tare da dabarun abokin ciniki ta hanyar Console System.
Bi hanya a hanyar haɗin bayanan da aka bayar don gwada ƙirar ƙiraample a cikin kayan aikin da aka zaɓa.
Bayanai masu alaƙa
- Gwada Low Latency E-Tile 40G Ethernet Intel FPGA IP Design a cikin Hardware a shafi na 9
- Nazari da Gyara Zane-zane tare da Console System
Gwajin Loopback na ciki
Gudun waɗannan matakan don yin gwajin madauki na ciki:
- Sake saita tsarin.
sys_reset_digital_analog - Nuna mitar agogo da matsayin PHY.
chkphy_status - Kunna gwajin madauki na ciki.
madauki - Nuna mitar agogo da matsayin PHY. An saita rx_clk zuwa 312.5 MHz kuma
rx_pcs_ready an saita zuwa 1.
chkphy_status - Fara janareta fakiti.
fara_pkt_gen - Dakatar da fakitin janareta.
tsaya_pkt_gen - Review adadin fakitin da aka watsa da karɓa.
chkmac_stats - Kashe gwajin madauki na ciki.
madauki
Gwajin Loopback na waje
Gudun waɗannan matakan don yin gwajin madauki na waje:
- Sake saita tsarin.
sys_reset_digital_analog - Nuna mitar agogo da matsayin PHY. An saita rx_clk zuwa 312.5 MHz kuma
rx_pcs_ready an saita zuwa 1. chkphy_status - Fara janareta fakiti.
fara_pkt_gen - Dakatar da fakitin janareta.
tsaya_pkt_gen - Review adadin fakitin da aka watsa da karɓa.
chkmac_stats
Low Latency E-Tile 40G Ethernet Design Exampda Rajista
Low Latency E-Tile 40G Ethernet Hardware Design Exampda Rajista taswira
Ya lissafa jeri na rijistar taswirar žwažwalwar ajiya don ƙirar kayan masarufiample. Kuna samun damar waɗannan rajistar tare da ayyukan reg_read da reg_write a cikin Tsarin Console.
| Kashe Magana | Nau'in Rijista |
| 0x300-0x3FF | PHY rajista |
| 0x400-0x4FF | TX MAC rajista |
| 0x500-0x5FF | RX MAC rajista |
| 0x800-0x8FF | Ƙididdiga Counter rajista - TX shugabanci |
| 0x900-0x9FF | Rijistar Counter Statistics - Hanyar RX |
| 0x1000-1016 | Fakitin Client rajista |
Fakitin Abokin Rijista
Kuna iya keɓance ƙirar ƙirar kayan aikin E-Tile 40G Low Latency Example ta shirye-shirye da abokin ciniki rajista.
| Addr | Suna | Bit | Bayani | Sake saita ƙimar HW | Shiga |
| 0 x1008 | Saita Girman Fakiti | [29:0] | Ƙayyade girman fakitin watsawa a cikin bytes. Waɗannan raƙuman suna da abubuwan dogaro ga rajistar PKT_GEN_TX_CTRL.
• Bit [29:16]: Ƙayyade iyakar girman fakiti a cikin bytes. Wannan yana aiki ne kawai ga yanayin haɓakawa. • Bit [13:0]: - Don ƙayyadaddun yanayin, waɗannan ragowa suna ƙayyade girman fakitin watsawa a cikin bytes. - Don yanayin haɓakawa, waɗannan ragowa suna ƙayyadad da haɓakar bytes don fakiti. |
0 x25800040 | RW |
| 0 x1009 | Sarrafa Lambar Fakiti | [31:0] | Ƙayyade adadin fakiti don aikawa daga janareta fakiti. | 0xA ku | RW |
| 0 x1010 | PKT_GEN_TX_C TRL | [7:0] | • Bit [0]: Ajiye.
• Bit [1]: Fakiti janareta ya kashe bit. Saita wannan bit zuwa ƙimar 1 don kashe janareta na fakiti, kuma sake saita shi zuwa ƙimar 0 don kunna janareta na fakiti. • Bit [2]: Ajiye. • Bit [3]: Yana da darajar 1 idan IP core yana cikin yanayin madauki na MAC; yana da ƙimar 0 idan abokin ciniki na fakiti yana amfani da janareta na fakiti. |
0 x6 | RW |
| ci gaba… | |||||
| Addr | Suna | Bit | Bayani | Sake saita ƙimar HW | Shiga |
| • Bit [5:4]:
- 00: Yanayin bazuwar - 01: Kafaffen yanayi - 10: Yanayin haɓaka • Bit [6]: Sanya wannan bit zuwa 1 don amfani da rajista na 0x1009 don kashe janareta na fakiti bisa ƙayyadaddun adadin fakiti don watsawa. In ba haka ba, ana amfani da bit [1] na rajistar PKT_GEN_TX_CTRL don kashe janareta na fakiti. • Bit [7]: - 1: Don watsawa ba tare da tazara tsakanin fakiti ba. - 0: Don watsawa tare da bazuwar tazara tsakanin fakiti. |
|||||
| 0 x1011 | Adireshin makoma ƙananan 32 bits | [31:0] | Adireshin wurin (ƙananan 32 bits) | 0x56780AD | RW |
| 0 x1012 | Adireshin makoma babba 16 bits | [15:0] | Adireshin zuwa (babban 16 bits) | 0 x1234 | RW |
| 0 x1013 | Adireshin tushe ƙananan 32 bits | [31:0] | Adireshin tushe (ƙananan 32 bits) | 0x43210AD | RW |
| 0 x1014 | Adireshin tushe babba 16 bits | [15:0] | Adireshin tushe (babba 16 bits) | 0 x8765 | RW |
| 0 x1016 | PKT_CL_LOOPB ACK_RESET | [0] | MAC loopback sake saiti. Saita zuwa ƙimar 1 don sake saita ƙira exampda MAC loopback. | 1 b0 ku | RW |
Bayanai masu alaƙa
Ƙananan Latency E-Tile 40G Ethernet Control and Status Register Descriptions Yana Siffanta Ƙananan Latency E-Tile 40G Ethernet IP core rajista.
Zane Exampda Alamar Interface
The Low Latency E-Tile 40G Ethernet testbench yana ƙunshe da kansa kuma baya buƙatar ku fitar da kowane siginar shigarwa.
Low Latency E-Tile 40G Ethernet Hardware Design Exampda Alamar Interface
| Sigina | Hanyar | Sharhi |
|
klk50 |
Shigarwa |
Ana gudanar da wannan agogon ta hanyar oscillator na allo.
• Tuƙi a 50 MHz akan allon Intel Stratix 10. • Tuƙi a 100 MHz akan allon Intel Agilex. Kayan aikin hardware exampLe yana tafiyar da wannan agogon zuwa shigar da IOPLL akan na'urar kuma ya saita IOPLL don fitar da agogon 100 MHz a ciki. |
| clk_ref | Shigarwa | Tuba a 156.25 MHz. |
| ci gaba… | ||
| Sigina | Hanyar | Sharhi |
|
cpu_sake saitin |
Shigarwa |
Yana sake saita ainihin IP. Ƙananan aiki. Yana fitar da sake saiti mai wuya na duniya csr_reset_n zuwa ainihin IP. |
| tx_serial[3:0] | Fitowa | Serial bayanan fitarwa na Transceiver PHY. |
| rx_serial[3:0] | Shigarwa | Serial bayanan shigar da Transceiver PHY. |
|
mai amfani_led[7:0] |
Fitowa |
Alamun matsayi. Tsarin kayan masarufi exampLe ya haɗa waɗannan ragowa don fitar da LEDs akan allon da aka yi niyya. Rago ɗaya ɗaya yana nuna ƙimar sigina masu zuwa da halayen agogo:
• [0]: Babban siginar sake saiti zuwa ainihin IP • [1]: Rarraba sigar clk_ref • [2]: Rarraba sigar clk50 • [3]: Rarraba nau'in agogon matsayi na 100 MHz • [4]: tx_lanes_stable • [5]: rx_block_lock • [6]: rx_am_lock • [7]: rx_pcs_ready |
Bayanai masu alaƙa
Hanyoyin sadarwa da Bayanin siginar Yana ba da cikakken kwatanci na ƙananan siginonin IP na ƙananan Latency E-Tile 40G Ethernet da mu'amalar da suke.
Ƙananan Latency E-Tile 40G Ethernet Intel FPGA IP Archives
Idan ba a jera sigar ainihin IP ba, jagorar mai amfani don sigar ainihin IP ta baya tana aiki.
| Intel Quartus Prime Version | IP Core Version | Jagorar Mai Amfani |
| 20.1 | 19.1.0 | Low Latency E-Tile 40G Ethernet Design ExampJagorar Mai Amfani |
Tarihin Bita na Takardu don Ƙananan Latency E-tile 40G Ethernet Design ExampJagorar Mai Amfani
| Sigar Takardu | Intel Quartus Prime Version | Sigar IP | Canje-canje |
| 2020.06.22 | 20.2 | 20.0.0 | Ƙara tallafin na'ura don na'urorin Intel Agilex. |
| 2020.04.13 | 20.1 | 19.1.0 | Sakin Farko. |
Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. Ana iya da'awar wasu sunaye da alamun a matsayin mallakin wasu.
Takardu / Albarkatu
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intel Low Latency E-Tile 40G Ethernet Intel FPGA IP Design Example [pdf] Jagorar mai amfani Low Latency E-Tile 40G Ethernet Intel FPGA IP Design Example, Low Latency, E-Tile 40G Ethernet Intel FPGA IP Design Example, Intel FPGA IP Design Example, IP Design Example |
