F-Tile Interlaken Intel FPGA IP Design Example

Jagoran Fara Mai Sauri

F-Tile Interlaken Intel® FPGA IP core yana ba da benci na simulation. A hardware zane exampwanda ke goyan bayan haɗawa kuma gwajin kayan masarufi zai kasance a cikin Intel Quartus® Prime Pro Edition software version 21.4. Lokacin da ka samar da zane exampHar ila yau, editan siga yana ƙirƙirar ta atomatik filewajibi ne don kwaikwaya, tattarawa, da gwada ƙira.
The testbench da zane exampLe yana goyan bayan yanayin NRZ da PAM4 don na'urorin F-tile. F-Tile Interlaken Intel FPGA IP core yana haifar da ƙiraampLes don haɗin haɗin gwiwar masu zuwa na adadin hanyoyi da ƙimar bayanai.

Haɗin IP mai Tallafin Adadin Layuka da ƙimar Bayanai
Ana samun goyan bayan haɗe-haɗe masu zuwa a cikin sigar software ta Intel Quartus Prime Pro 21.3. Duk sauran haɗe-haɗe za a tallafawa a cikin sigar Intel Quartus Prime Pro Edition na gaba.

Yawan Layuka	Adadin Layin (Gbps)
	6.25	10.3125	12.5	25.78125	53.125
4	Ee	-	Ee	Ee	-
6	-	-	-	Ee	Ee
8	-	-	Ee	Ee	-
10	-	-	Ee	Ee	-
12	-	Ee	Ee	Ee	-

Hoto 1. Matakan Ci gaba don Zane Example

Lura: Hardware Hardware da Gwaji za a samu a cikin Intel Quartus Prime Pro Edition software version 21.4.
F-Tile Interlaken Intel FPGA IP core design example yana goyan bayan fasalulluka masu zuwa:

• TX na ciki zuwa yanayin madauki na RX
• Yana haifar da ƙayyadaddun fakiti masu girman kai ta atomatik
• Asalin damar duba fakiti
• Ikon yin amfani da Console System don sake saita ƙira don manufar sake gwadawa

Hoto 2.Hanyar Block-High-Level

Bayanai masu alaƙa

• F-Tile Interlaken Intel FPGA IP Jagorar Mai Amfani
• F-Tile Interlaken Intel FPGA IP Bayanan Bayanin Sakin

Bukatun Hardware da Software

Don gwada tsohonampDon ƙira, yi amfani da hardware da software masu zuwa:

• Intel Quartus Prime Pro Edition software 21.3
• Tsarin Console
• Na'urar kwaikwayo mai goyan baya:
  • Bayanan Bayani na VCS*
  • Rahoton da aka ƙayyade na VCS MX
  • Siemens* EDA ModelSim* SE ko Questa*

Lura:  Hardware goyon bayan zane exampZa a samu a cikin Intel Quartus Prime Pro Edition software version 21.4.

Samar da Zane

Hoto na 3. Tsari

Bi waɗannan matakan don samar da ƙirar example da testbench:

1. A cikin Intel Quartus Prime Pro Edition software, danna File ➤ Sabon Project Wizard don ƙirƙirar sabon aikin Intel Quartus Prime, ko danna File ➤ Bude Project don buɗe aikin Intel Quartus Prime da ke gudana. Mayen yana tambayarka don saka na'ura.
2. Ƙayyade dangin Agilex na na'urar kuma zaɓi na'urar tare da F-Tile don ƙirar ku.
3. A cikin Catalog na IP, gano wuri kuma danna F-Tile Interlaken Intel FPGA IP sau biyu. Sabuwar taga Bambancin IP yana bayyana.
4. Ƙayyade sunan babban matakin don bambancin IP ɗin ku na al'ada. Editan siga yana adana saitunan bambancin IP a cikin a file mai suna .ip.
5. Danna Ok. Editan siga ya bayyana.

Hoto 4. Exampda Design Tab

6. A kan shafin IP, ƙayyade sigogi don bambancin ainihin IP ɗin ku.
7. Akan ExampDon Zane shafin, zaɓi zaɓin Simulation don ƙirƙirar bench.
Lura: Zaɓin haɗin gwiwa don hardware example zane, wanda zai kasance a cikin Intel Quartus Prime Pro Edition software version 21.4.
8. Don Ƙirƙirar HDL Format, duka Verilog da VHDL zaɓi yana samuwa.
9. Danna Generate Exampda Design. Zaɓi ExampTagar Zane Directory ya bayyana.
10. Idan kana so ka gyara zane examphanyar directory ko suna daga abubuwan da aka nuna (ilk_f_0_example_design), bincika zuwa sabuwar hanya kuma rubuta sabon ƙira exampda directory name.
11. Danna OK.

Lura: A cikin F-Tile Interlaken Intel FPGA IP ƙiraampHar ila yau, ana aiwatar da SystemPLL ta atomatik, kuma an haɗa shi zuwa F-Tile Interlaken Intel FPGA IP core. Hanyar matsayi na SystemPLL a cikin ƙira exampda ni:

example_design.test_env_inst.test_dut.dut.pll

The SystemPLL a cikin zane exampLe yana raba agogon tunani iri ɗaya na 156.26 MHz kamar Mai Canjawa.

Tsarin Jagora

F-Tile Interlaken Intel FPGA IP core yana haifar da masu zuwa files don zane exampda:
Hoto 5. Tsarin Jagora

Tebur 2. Tsarin Hardware Example File Bayani
Wadannan files suna cikinample_installation_dir>/ilk_f_0_example_design directory.

File Sunaye	Bayani
example_design.qpf	Intel Quartus Prime aikin file.
example_design.qsf	Saitunan ayyukan Intel Quartus Prime file
example_design.sdc jtag_time_template.sdc	Ƙuntataccen Ƙira na Synopsys file. Kuna iya kwafa da gyara don ƙirar ku.
sysconsole_testbench.tcl	Babban file don samun damar System Console

Lura: Hardware goyon bayan zane exampZa a samu a cikin Intel Quartus Prime Pro Edition software version 21.4.

Tebur 3. Testbench File Bayani

Wannan file yana cikinample_installation_dir>/ilk_f_0_example_design/ example_design/rtl directory.

File Suna	Bayani
saman_tb.sv	Babban matakin gwajin benci file.

Tebur 4. Rubutun Testbench

Wadannan files suna cikinample_installation_dir>/ilk_f_0_example_design/ example_design/testbench directory

File Suna	Bayani
run_vcs.sh	Rubutun Synopsys VCS don gudanar da gwajin benci.
run_vcsmx.sh	Rubutun Synopsys VCS MX don gudanar da gwajin benci.
run_mentor.tcl	Siemens EDA ModelSim SE ko Rubutun Questa don gudanar da gwajin benci.

Simulating da Design Exampda Testbench

Hoto 6. Tsari

Bi waɗannan matakan don kwaikwaya testbench:

1. A saurin umarni, canza zuwa littafin simulations na testbench. Hanyar jagora ita ceample_installation_dir>/ misaliample_design/ testbench.
2. Gudanar da rubutun simintin don goyan bayan na'urar kwaikwayo na zaɓinku. Rubutun yana tattarawa kuma yana gudanar da testbench a cikin na'urar kwaikwayo. Rubutun ku ya kamata ya duba cewa SOP da EOP ƙidaya sun dace bayan an gama simulation.

Tebur 5. Matakan Gudun Kwaikwayo

Na'urar kwaikwayo	Umarni
VCS	A cikin layin umarni, rubuta:   sh run_vcs.sh
Farashin VCS MX	A cikin layin umarni, rubuta:   sh run_vcsmx.sh
ModelSim SE ko Questa	A cikin layin umarni, rubuta:   vsim -do run_mentor.tcl Idan kun fi son yin kwaikwayo ba tare da kawo ModelSim GUI ba, rubuta:   vsim -c -do run_mentor.tcl

3. Yi nazarin sakamakon. Simulation mai nasara yana aikawa da karɓar fakiti, kuma yana nuna "GWAJI WUCE".

The testbench ga zane exampya kammala ayyuka masu zuwa:

• Yana ƙaddamar da F-Tile Interlaken Intel FPGA IP core.
• Yana buga halin PHY.
• Yana duba aiki tare da metaframe (SYNC_LOCK) da iyakoki (katange) (WORD_LOCK).
• Yana jira a kulle da daidaita wayoyi guda ɗaya.
• Fara watsa fakiti.
• Duba kididdigar fakiti:
  • Kurakurai CRC24
  • SOPs
  • EOPs

Mai zuwa sampLe fitarwa yana kwatanta nasarar gwajin simulation:

Haɗa Zane Example

1. Tabbatar da tsohonample zane tsara ya cika.
2. A cikin software na Intel Quartus Prime Pro Edition, buɗe aikin Intel Quartus Primeample_installation_dir>/ misaliample_design.qpf>.
3. A cikin menu na sarrafawa, danna Fara Tari.

Zane Example Bayanin

Zane example yana nuna ayyukan Interlaken IP core.

Zane ExampAbubuwan da aka gyara

The example zane yana haɗa tsarin da agogon tunani na PLL da abubuwan ƙira da ake buƙata. The example zane yana daidaita ainihin IP a cikin yanayin madauki na ciki kuma yana haifar da fakiti akan hanyar sadarwar mai amfani ta IP core TX. Babban IP ɗin yana aika waɗannan fakiti akan hanyar madauki na ciki ta hanyar mai karɓa.
Bayan mai karɓar ainihin IP ɗin ya karɓi fakiti akan hanyar madauki, yana aiwatar da fakitin Interlaken kuma yana watsa su akan hanyar musayar bayanan mai amfani na RX. The example zane yana bincika cewa fakitin da aka karɓa kuma sun watsa wasan.
F-Tile Interlaken Intel IP zane example ya ƙunshi abubuwa masu zuwa:

1. F-Tile Interlaken Intel FPGA IP core
2. Fakiti Generator da Fakiti Checker
3. Bayanin F-Tile da Tsarin PLL yana kulle Intel FPGA IP core

Siginonin Sadarwa

Tebur 6. Zane Exampda Alamar Interface

Sunan tashar jiragen ruwa	Hanyar	Nisa (Bits)	Bayani
mgmt_clk	Shigarwa	1	Shigar da agogon tsarin. Mitar agogo dole ne ya zama 100 MHz.
pl_ref_clk	Shigarwa	1	Agogon magana mai jujjuyawa. Yana fitar da RX CDR PLL.
rx_pin	Shigarwa	Yawan hanyoyi	fil ɗin bayanan mai karɓar SErdES.
tx_pin	Fitowa	Yawan hanyoyi	Aika fil ɗin bayanan SErdES.
rx_pin_n (1)	Shigarwa	Yawan hanyoyi	fil ɗin bayanan mai karɓar SErdES.
tx_pin_n(1)	Fitowa	Yawan hanyoyi	Aika fil ɗin bayanan SErdES.
mac_clk_pll_ref	Shigarwa	1	Dole ne PLL ke tafiyar da wannan siginar kuma dole ne yayi amfani da tushen agogo iri ɗaya wanda ke tafiyar da pll_ref_clk. Ana samun wannan sigina kawai a cikin bambancin na'urar yanayin PAM4.
usr_pb_reset_n	Shigarwa	1	Sake saitin tsarin.

(1) Akwai kawai a cikin bambance-bambancen PAM4.

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka.
*Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

Rajista taswira

Lura:

• Zane Exampadireshin rajista yana farawa da 0x20** yayin da adireshin IP na Interlaken ya fara da 0x10**.
• Adireshin rajista na F-tile PHY yana farawa da 0x30** yayin da adireshin F-tile FEC yana farawa da 0x40**. Ana samun rijistar FEC a yanayin PAM4 kawai.
• Lambar shiga: RO — Karanta Kawai, da RW — Karanta/Rubuta.
• Na'urar wasan bidiyo na tsarin tana karanta zanen exampLe yayi rijista kuma yayi rahoton matsayin gwajin akan allon.

Tebur 7. Zane Exampda Rajista taswira

Kashewa	Suna	Shiga	Bayani
8'h00	Ajiye
8'h01	Ajiye
8'h02	Sake saitin tsarin PLL	RO	Masu bin ragowa suna nuna buƙatar sake saitin PLL na tsarin kuma yana ba da ƙimar: • Bit [0] - sys_pll_rst_req • Bit [1] - sys_pll_rst_en
8'h03	Hanyar RX ta daidaita	RO	Yana nuna daidaita layin RX.
8'h04	KALMOMI a kulle	RO	[NUM_LANES–1:0] - Kalma (katange) tantance iyakoki.
8'h05	A kulle sync	RO	[NUM_LANES–1:0] - Aiki tare da metaframe.
8'h06-8h09	Ƙididdigar kuskuren CRC32	RO	Yana nuna ƙidaya kuskuren CRC32.
8 h0a	Ƙididdigar kuskuren CRC24	RO	Yana nuna ƙidaya kuskuren CRC24.
8 h0b	Alamar ambaliya/karɓar ruwa	RO	Abubuwan da ke biyo baya suna nuna: • Bit [3] - TX siginar ƙarƙashin ruwa • Bit [2] – TX siginar ambaliya • Bit [1] – RX siginar ambaliya
8 h0c	Ƙididdigar SOP	RO	Yana nuna adadin SOP.
8 h0d	Adadin EOP	RO	Yana nuna adadin EOP
8 h0e	Ƙidaya kuskure	RO	Yana nuna adadin kurakurai masu zuwa: • Rashin daidaita layi • Kalmar sarrafa ba bisa ka'ida ba • Tsarin ƙira ba bisa ka'ida ba • Rashin SOP ko alamar EOP
8 h0f	aika_data_mm_clk	RW	Rubuta 1 zuwa bit [0] don kunna siginar janareta.
8'h10	Kuskuren dubawa		Yana nuna kuskuren mai duba. (Kuskuren bayanan SOP, Kuskuren lambar tashar, da kuskuren bayanan PLD)
8'h11	Kulle tsarin PLL	RO	Bit [0] yana nuna alamar kulle PLL.
8'h14	Farashin TX SOP	RO	Yana nuna adadin SOP wanda janareta na fakiti ya samar.
8'h15	Farashin TX EOP	RO	Yana nuna adadin EOP wanda janareta na fakiti ya samar.
8'h16	Fakitin ci gaba	RW	Rubuta 1 zuwa bit [0] don kunna fakitin ci gaba.
ci gaba…

Kashewa	Suna	Shiga	Bayani
8'h39	Ƙididdigar kuskuren ECC	RO	Yana nuna adadin kurakuran ECC.
8'h40	ECC ta gyara ƙidayar kuskure	RO	Yana nuna adadin kurakuran ECC da aka gyara.
8'h50	tile_tx_rst_n	WO	Sake saitin tayal zuwa SRC don TX.
8'h51	tile_rx_rst_n	WO	Sake saitin tayal zuwa SRC don RX.
8'h52	tile_tx_rst_ack_n	RO	Tabbatar da sake saitin tayal daga SRC don TX.
8'h53	tile_rx_rst_ack_n	RO	Tabbatar da sake saitin tayal daga SRC don RX.

Sake saiti

A cikin F-Tile Interlaken Intel FPGA IP core, kuna fara sake saiti (reset_n=0) kuma ku riƙe har sai ainihin IP ɗin ya dawo da sake saiti (reset_ack_n=0). Bayan an cire sake saitin (reset_n=1), amincewar sake saitin zai dawo zuwa yanayin farko
(reset_ack_n=1). A cikin zane example, rajistar rst_ack_sticky tana riƙe da tabbacin sake saiti sannan kuma yana haifar da cire sake saiti (reset_n=1). Kuna iya amfani da madadin hanyoyin da suka dace da bukatun ƙirar ku.

Muhimmi: A kowane yanayi inda ake buƙatar madauki na ciki, dole ne ku saki TX da RX na F-tile daban a cikin takamaiman tsari. Koma zuwa rubutun na'ura mai kwakwalwa don ƙarin bayani.

Hoto 7.Sake saita Jeri a Yanayin NRZ

Hoto 8.Sake saitin jeri a Yanayin PAM4

F-Tile Interlaken Intel FPGA IP Design ExampRukunin Rubutun Jagorar Mai Amfani

Idan ba a jera sigar ainihin IP ba, jagorar mai amfani don sigar ainihin IP ta baya tana aiki.

Intel Quartus Prime Version	IP Core Version	Jagorar Mai Amfani
21.2	2.0.0	F-Tile Interlaken Intel FPGA IP Design ExampJagorar Mai Amfani

Tarihin Bita na Takardu don F-Tile Interlaken Intel FPGA IP Design ExampJagorar Mai Amfani

Sigar Takardu	Intel Quartus Prime Version	Sigar IP	Canje-canje
2021.10.04	21.3	3.0.0	• Ƙara tallafi don sabbin hanyoyin haɗin kan layi. Don ƙarin bayani, koma zuwa Tebura: Haɗin IP mai Tallafawa na Yawan Layuka da ƙimar Bayanai. • An sabunta lissafin na'urar kwaikwayo mai goyan baya a cikin sashe: Bukatun Hardware da Software. • Ƙara sabbin rajistar sake saitin a sashe: Rajista taswira.
2021.06.21	21.2	2.0.0	Sakin farko.

Takardu / Albarkatu

intel F-Tile Interlaken Intel FPGA IP Design Example [pdf] Jagorar mai amfani F-Tile Interlaken Intel FPGA IP Design Example, F-Tile, Interlaken Intel FPGA IP Design Example, Intel FPGA IP Design Example, IP Design Example, Design Example

Magana

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